Introduction 1 Table of Contents 1.1 Library Description .............................................................................................. 1-1 1.2 Features .............................................................................................................. 1-2 1.3 EDA Support ....................................................................................................... 1-4 1.4 Product Family..................................................................................................... 1-4 1.4.1 Analog Core Cells...................................................................................... 1-4 1.4.2 Internal Macrocells .................................................................................... 1-12 1.4.3 Compiled Macrocells ................................................................................. 1-12 1.4.4 Input/Output Cells ...................................................................................... 1-14 1.5 Timings................................................................................................................ 1-16 1.6 Delay Model ........................................................................................................ 1-22 1.7 Testability Design Methodology........................................................................... 1-24 1.8 Maximum Fanouts............................................................................................... 1-27 1.9 Packages Capability by Lead Count ................................................................... 1-34 1.10 Power Dissipation ............................................................................................. 1-36 1.11 VDD/VSS Rules and Guidelines .......................................................................... 1-39 1.12 Crystal Oscillator Considerations...................................................................... 1-45 Introduction 1.1 Library Description 1.1 Library Description Samsung ASIC offers STD111 as 0.25um CMOS standard cell library. Samsung's 0.25um cell-based logic process providing up to 5 layers of interconnect metal with various I/O pad-pitch options such as 70um pitch pad and 80um pitch pad. STD111 which reduced power dissipation and system cost by merging the logic and IPs as a whole and connecting internally from logic to memory data bus is ideal for high-performance products such as graphics controller, projector, portable CD and so on. STD111 can support up to six million gate counts of logic providing 75% of usable gate. STD111 is 25% faster than 0.35um library STD90. Logic density is 1.7 times greater than that of STD90. The power consumption of compiled memory is 90% smaller than STD90. STD111 also supports fully user-configurable compiled memory and datapath elements. Each element is provided as a compiler. Two different types of compiled memories in STD111 are available to support memories suitable to high-density and low-power applications. To support mixed voltage environments, 2.5V, 3.3V drive and 5V-tolerant IO cells are available. LVTTL, LVCMOS, PCI, OSC, AGP, PECL, HSTL, LVDS and USB buffers are supported. To better support a system-on-chip design style, various core cells are available including processor cores like ARM7TDMI/ARM9TDMI/ ARM920T/ARM940T from ARM, Teaklite from DSPG. The STD111 supports data transmission and communication core such as USB, IEEE1284 and UART. The list of analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC and PLL with various bits and frequency ranges. Samsung design methodology offers an comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis and timing driven layout. Its advanced characterization flow provides accurate timing data and robust delay models for a 0.25um very deep-submicron technology. Advanced verification methods like static timing analysis and formal verification provide an effective verification methodology with a variety of simulators and cycle based simulation. Samsung DFT methodology supports scan design, BIST and JTAG boundary scan. Samsung provides a full set of test-ready IPs with an efficient core test integration methodology. Samsung ASIC 1-1 STD111 1.2 Features 1.2 Features Introduction * * * * * * * * * * STD111 2.5V standard cell library including processor and analog cores 0.25um five layer metal(from four layer metal option) CMOS technology - Logic, processor and analog High basic cell usages - Up to 6 million gates - Maximum usage: 75% for five layer metal High speed - Typical 2-input NAND gate delay (ND2D4): 68ps (F/O=2 + WL (0.02pF)) Operation temperature (TA) - Commercial range: 0C to +70C - Industrial range: -40C to +85C Digital cores usages - Hard-macro: ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, Teaklite - Soft-macro: AMBA, DMA Controller, SDRAM Controller, Interrupt Controller, IIC, WDT, RTC, USB, IrDA, UART (16C450, 16C550), Fast Ethernet MAC, P1394a LINK, RS Decoder, Viterbi Decoder Analog cores usages - Ultra low voltage analog core (2.5V and 1.8V) available - Analog core supply voltage: 2.5V analog core: 2.5V 5% 1.8V analog core: 1.8V 5% - ADC: 8bit (30M, 2.5V), 10bit ((30M, 100M, 2.5V), (250K, 20M, 1.8V)), 12bit (200K, 20M, 2.5V) - DAC: 8bit (2M, 2.5V), 10bit ((300M, 2.5V), (2M, 1.8V)), 12bit ((2M, 2.5V), (80M, 1.8V)) - CODEC: 8bit (8K~11K), 16bit (44.1K) - PLL: 25M ~ 300M (FSPLL, 2.5V), 1G (PLL, 2.5V), 20M ~ 170M (FSPLL, 1.8V) - Others: 300M (RAMDAC+PLL) Fully user-configurable Static RAMs and ROMs - High-density and low-power memory available - Duty-free cycle in synchronous memory available - 2-bank architecture available - Flexible aspect ratio available - Up to 256K-bit single-port SRAM available. - Up to 128K-bit dual-port SRAM available. - Up to 512K-bit diffusion and metal-2 ROM available. - Up to 16K-bit multi-port register file available. - Up to 32K-bit FIFO available. Fully configurable datapath macrocells - 4 ~ 64 bit adder available - 4 ~ 64 bit barrel shifter available - 6 ~ 64 bit multiplier with 1-stage pipeline available - Various output driver strength available - A tightly integrate apollo, Avant!, design environment I/O cells - 2.5V/3.3V and 5V tolerant IO - 3-level (high, medium, no) slew rate control - 1/2/4/6/8/10/12mA available for 3.3V and 2.5V output buffers - 1/2/3mA available for 5V-tolerant output buffers 1-2 Samsung ASIC Introduction 1.2 * * * Features IO IP available - PCI ((33MHz, 66MHz, 3.3V), (33MHz, 3.3/5V tolerant)) - USB (full speed/low speed) - SSTL2 (DDR SDRAM interface, up to 200MHz) - AGP (AGP2.0 Compliant, 66MHz@1X,133MHz@2X, 266MHz@4X) - PECL (2.5V interface, up to 400MHz) - HSTL (class1, class2, 30MHz) - LVDS (3.3V(2.5V optional) interface, 300MHz) Various package options - QFP, thin QFP, power QFP, plastic BGA, super BGA, plastic leaded chip carrier, etc. Fully integrated CAD software and EDA support - Logic synthesis: Synopsys Design Compiler - Logic simulation: Cadence Verilog-XL, Cadence NC-Verilog, Viewlogic ViewSim, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VSS, Synopsys VCS - Scan insertion and ATPG: Synopsys TestGen, Synopsys Test Compiler, Mentor Fastscan - Static timing analysis: Synopsys PrimeTime, Synopsys MOTIVE - RC analysis: Avant! Star-RC - Power analysis: Synopsys DesignPower, CubicPower (ln-House Tool) - Formal verification: Synopsys Formality, Chrysalis Design VERIFYer, Verplex Tuxedo-LEC - Fault simulation: Cadence Verifault, SuperTest (In-House Tool) - Delay calculator: CubicDelay (In-House Tool) * STD111 contains 12 user selectable clock tree cells(CTC). At the pre-layout design stage, these will be used as the cells which represent actual clock tree informatin of P&R. The key features of new Samsung ASIC CTS flow are as follows: - 12 user selectable clock tree cells (CTC) for STD111 - Good pre-layout and post-layout correlation - No customer netlist modification - Accurate post-layout back-annotation mechanism - Insertion delay, skew, transition time management - Clock tree information file generation - Cover 100 to 30,000 fanouts and up to 1M gate count for CTS spanning block (GCCSB) - Tightly coupled with Samsung in-house delay calculator, CubicDelay Gated CTS support - Hierarchical/Flatten verilog, edif interface for P&R For more detail information for CTC flow, refer to "CTC flow guideline for CubicDelay" included in Samsung ASIC design kit. Samsung ASIC 1-3 STD111 1.3 EDA Support 1.3 EDA Support Introduction Samsung ASIC provides an efficient solution for multi-million gate ASICs in very deep submicron (VDSM) technology. For large system-on-chip (SOC) type designs, static verification methodology (static timing analysis and formal verification) will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. Our Design-for-Test (DFT) methodology and service take you through all phases of test insertion, test pattern generation and fault grading to get high test coverage. STD111 supports a rich collection of industry-standard EDA tools from Cadence, Synopsys, Mentor graphics, and Avant! on multiple design platforms such as Solaris and HP. Customers are allowed to choose among the industry-leading EDA tools from design capture, synthesis, simulation, and DFT to layout. Several powerful proprietary software tools are seamlessly integrated in our design kits to improve your product quality. For high simulation accuracy, STD111 uses a proprietary delay calculator. Cell delay is calculated based on a matrix of delay parameters for each macrocell, and signal interconnect delay is calculated based on the RC tree analysis. 1.4 Product Family STD111 library include the following design elements: Analog core cells Digital core cells Internal macrocells Compiled macrocells Input/Output cells. 1.4.1 ANALOG CORE CELLS Introduction to Analog Cores Samsung ASIC is one of the leading suppliers of cell based mixed analog and digital designs. As a leading supplier of mixed analog and digital designs, Samsung ASIC has more analog design experience than any other vendors. Analog has been and will continue to be a part of the strategic focus at Samsung ASIC. Analog design is a part of the total Samsung ASIC integrated design system. Workstation symbols are supplied for analog cells and are entered as part of the design by the customer or design center. Samsung ASIC uses basically the same automatic layout and verification tools for analog cells as for digital cells. Analog designs are processed on the same production line as digital designs. Samsung's analog core family comprises ADC,DAC,PLL and sigma-delta ADC/ DAC, and their brief functional descriptions are introduced below. [data sheets for all analog cores available] Analog-to-Digital Converters Analog-to-digital converters provide the link between the analog world and digital systems. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. An A/D converter produces a digital output, D, as a function of the analog input, A: D = f(A) While the input can assume an infinite number of values, the output can be selected from only a finite set of codes given by the converter's output word length(i.e, resolution). Thus, the ADC must approximate each input level with one of these codes, this process is so called 'quantization'. STD111 1-4 Samsung ASIC Introduction 1.4 Product Family In a digital system the amplitude is quantized into discrete steps, and at the same time the signal is sampled at discrete time intervals. This time interval is called sampling time or sampling frequency. After sampling and quantization process, the analog signal(A) becomes digital output (D). Digital-to-Analog Converters The D/A converters are the digital-to-analog conversion circuits, which are also called DACs. They can be considered as decoding devices that accept digitally coded signals and provide analog output in the form of currents or voltages. In this manner, they provide an interface between the digital signal of the computer systems and continuous signals of analog world. They are employed in a variety of applications, from CRT display systems and voice sythesizers to automatic test systems, digital controlled attenuators, and process control actuators. In addition, they are key components inside most A/D converters. Figure 1 shows the functional block diagram of a basic D/A converter system. The input to the D/A converter is a digital word, made up a stream of binary bits comprised of 1's and 0's. The output analog quantity A, which can be a voltage or current, is related to the input as b1 b2 bn A = KVREF -----1- + -----2- + ... + -----n2 2 2 where K is a scale factor, VREF is a reference voltage, n is the total number of bits, and b1,b2,...,bn are the bit coefficients, which are quntized to be a 1 or a 0. As a function of the input binary word which determines the bit coefficients, the output exhibits 2n discrete voltage level ranging from zero to a maximum value of n 2 -1 Vo(max)= VREF ------------n 2 with a minimum step change Vo given as V REF Vo= ------------\ n 2 Figure 1-1. Digital Data Input Functional Block Diagram of Basic D/A Converter b1 b2 b3 D/A Converter Analog Output bn Samsung ASIC 1-5 STD111 1.4 Product Family Introduction Sigma-Delta ADC/DAC VLSI offers high speed and high density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range). Hence, an exchange of digital complexity and of resolution in time for resolution in signal amplitude is needed. So good solution is over-sampling data converter. Oversampling sigma-delta converter is used in slow speed (audio band) application because of process limit. It's noise shaping (sigma-delta) feature make high resolution about max. SND=90~100dB In ADC path, analog single input is converted to differential signal with antialiasing filtering through anti-aliasing filter block. And sigma-delta modulator converts the signal into oversampled noise-shaping 1bit PDM (Pulse Density Modulation). Following digital decimation filter reject the out of band noise and outputs 16bits high resolution digital data with down sampled to Fs rate. In DAC path, digital input data is oversampled by interpolation filter and it is converted to noiseshaped 1bit PDM through digital sigma-delta modulator. Analog SC-post-filter rejects the out of band noise. And anti-image filter rejects sampling images and outputs single analog signal with high resolution. Phase Locked Loop Samsung's PLL cores implemented as an analog function provide frequency multiplication capabilities and enable system designers to synchronize ASIC chip-level clock networks with a common reference signal. In the past, designers wishing to incorporate a PLL into a digital design environment had only two options: (1) A special mixed-signal process to incorporate analog functions onto the chip (2) An all digital PLL that can be incorporated into a standard digital process. However, a mixed-signal process is too expensive to be a feasible solution. On the other hand digital PLLs typically require huge silicon area and exhibits poor locking time despite their high accuracy. Differing from the previous solutions, Samsung's PLL cores can be implemented on standard digital CMOS process while functioning as an analog PLL. Samsung's PLL cores: * Require only a few off-chip passive components for the whole function * Remove the need for an expensive mixed-signal process * Provide faster locking time than all digital PLLs * Present low jitter characteristics Glossary by Core Families 1. Digital-to-Analog Converter 1. Resolution - An n-bit binary converter should be able to provide 2n distinct and different analog output values corresponding to the set of n-bit binary words. A converter that satisfies this criterion is said to have resolution of n bits. The smallest output change that can be resolved by a linear DAC is 2-n of the full-scale span. 2. Accuracy - Error of a D/A converter is the difference between the actual analog output and the output that is expected when a given digital code is applied to the converter. Source of error include gain error, offset error, linearity errors and noise. Error is usually commensurate with resolution, less than 2-(n+1), or 1/2 LSB of full scale. STD111 1-6 Samsung ASIC Introduction 1.4 Figure 1-2. Product Family Error of D/A Converter Analog Output Analog Output Actual Gain Error Ideal Ideal Actual Offset Error Digital Input Digital Input 3. LSB (Least-Significant Bit) - In a system in which a numerical magnitude is represented by a series of binary digits, the LSB is that bit that carries the smallest value or weight. It represents the smallest analog change that can be resolved by an n-bit converter. LSB (Analog Value) = FSR/2n FSR = Full-Scale Range, n = number of bits 4. MSB (Most-Significant Bit) - The binary digit with the largest numerical weighting. Normally, the MSB of a digital word has a weighting of 1/2 the full range. 5. Compliance-Voltage Range - For a current output DAC, the maximum range of(output) terminal voltage for which the device will provide the specified currentoutput characteristics. 6. Glitch - A glitch is a switching transient appearing in the output during a code transition. Its value is expressed as a product of voltage (V*ns) or current (mA*ns) and time duration or charge transferred. 7. Harmonic Distortion (and Total Harmonic Distortion) - The DAC is driven by the digitized representation of sine wave. The ratio of the RMS sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second through fifth. 2 2 2 2 12 ( V2 + V3 + V4 + V5 ) THD = 20log --------------------------------------------------------------V1 V1: RMS amplitude of the fundamental 8. Signal-to-Noise Ratio (SNR) - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follows the theoretical formula; S/Nmax = 6.02N + 1.76dB 9. Slew Rate - Slew rate of a device or circuit is a limitation in the rate of change of output voltage, usually imposed by some basic circuit consideration such as limited current to charge of capacitor. Amplifiers with slew rate of a few V/s are common and moderate in cost. Slew rates greater than about 75 V/s are usually seen only in more sophisticated (and expensive) devices The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output (if one is used). Samsung ASIC 1-7 STD111 1.4 Product Family Introduction 10. Settling Time - The time required, following a prescribed data change from the 50% point of the login input change, for the output of a DAC to reach and to remain within a given fraction (usually 1/2lsb) of the final value. Typical prescribed changes are full scale, 1MSB and 1LSB at a major carry. Settling time of current-output DACs is quite fast. The major share of settling time of a voltageoutput DAC is usually contributed by the settling time of the output op-amp circuit. Figure 1-3. Setting Time +V0 V0 -V0 Slew Rate 1 Slewing Setting Time to V0 Final Setting 11. Power-Supply Sensitivity -The sensitivity of a converter to changes in the power-supply voltages is normally expressed in terms of percent-of-full-scale change in analog output value (of fractions of 1LSB) for a 1% dc change in the power supply. Power supply sensitivity may also expressed in relation to a specified dc shift of supply voltage. A converter may be considered "good" if the change in reading at full scale does not exceed 1/2LSB for 3% change in power supply. Even better specs are necessary for converters designed for battery operation. 12. ILE (integral Linearity Error) - Linearity error of a converter, expressed in %, ppm of full-scale range or multiples of 1LSB, is a deviation of the analog values in a plot of the measured conversion relationship from a straight line. The straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to equalize maximum positive and negative deviation of the actual transfer characteristics from this straight line; or it can be a straight line passing through the endpoints of the transfer characteristic endpoints of the transfer characteristic after they have been calibrated (sometimes referred to as "endpoint" linearity). Endpoint linearity error is similar to relative accuracy error. For multiplying D/A converters, the analog linearity error, at a specified digital code, is defined in the same way as for multipliers, by deviation from a "best straight line" through the plot of the analog output-input response. 13. DLE (Differential Linearity Error) - Any two adjacent digital codes should result in measured output values that are exactly 1LSB apart (2-n of full scale for an n-bit converter). Any deviation of the measured "step" from the ideal difference is called differential linearity error expressed in multiplies of 1LSB. It is an important specification because a differential linearity error greater than 1LSB can lead to non-monotonic response in a D/A converter and missed codes in an A/D converter. 14. Monotonic - A DAC is said to be monotonic if the output either increases or remains constant as the digital input increases with the result that the output will always be a single-valued function of the input. The specification "monotonic" STD111 1-8 Samsung ASIC Introduction 1.4 Product Family (over a given temperature range) is sometimes substituted for a differential nonlinearity specification since differential nonlinearity less than 1LSB is a sufficient condition for monotonic behaviour. 2. Analog-to-Digital Converter 1. ILE (Integral Linearity Error: INL) - Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". The point used as "zero" occurs 1/2LSB before the first code transition. "Full scale" is defined as a level 1 1/2LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. 2. DLE (Differential Linearity Error: DNL) - An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes are guaranteed. 3. Offset Error - The first transition should occur at a level 1/2LSB above "zero". Offset is defined as the deviation of the actual first code transition from that point. 4. Gain Error - The first code transition should occur for an analog value 1/2LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. 5. Pipeline Delay (Latency) - The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle. 6. Effective Number of Bits (ENOB) - This is a measure of a device's dynamic performance and may be obtained from the SNDR or from a sine wave curve test fit according to the following expression: ENOB = SNDR - 1.76/6.02 ENOB = N-log2[RMS error (actual) / RMS error (ideal)] 7. Analog Bandwidth - The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. 8. Aperture Delay - The delay between the sampling clock and the instant the analog input signal is sampled. 9. Aperture Jitter - The sample to sample variation in aperture delay. 10. Bit Error Rate (BER) - The number of spurious code errors produced for any given input sine wave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sine wave. 11. Signal to Noise Ratio - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follow the theoretical formula; S/Nmax = 6.02N + 1.76dB Samsung ASIC 1-9 STD111 1.4 Product Family Introduction 3. Phase Locked Loop 1. Lock Time - The time it takes the PLL to lock onto the system clock. Fast or slow lock time may be controlled by the loop filter characteristics. The loop filter characteristics are controlled by varying the R and C components. (Remember that R and C define the damping-factor as well) 2. Phase Error - The phase difference between the feedback clock signal and the system signal clock. 3. Clock Jitter - The deviations in a clock's output transitions from their ideal positions define the clock jitter. Jitter is sometimes specified as an absolute value in nanoseconds. All jitter measurement are made at a specified voltage. 1) Cycle-to-Cycle Jitter: The change in a clock's output transition from its corresponding position in the previous cycle. This kind of jitter is the most difficult to measure and usually requires a time-interval analyzer Figure 1-4. Cycle-to-Cycle Jitter t1 t2 t3 Clock Noise: jitter J1 = t2-t1 jitter J2 = t3-t2 : The maximum of such values over multiple cycles (J1,J2...) is the max. cycle-tocycle jitter. 2) Period Jitter: Period jitter measures the maximum change in a clock's output transition from its ideal position. You can use period-jitter measurements to calculate timing margins in systems. Figure 1-5. Period Jitter ideal cycle: t1 Clock Jitter 3) Long-term Jitter: Long-term jitter measures the maximum change in a clock's output transition from its ideal position over many cycles. How many cycles depends on the application and the frequency. A classic example of system affected by long-term jitter is a graphics card driving a CRT 4) Power Down Mode: PLL state in which the quiescent current is lowered to a very low level to conserve power. 5) Synthesize clock: a system clock may run at a relatively low rate compared to system components. A CPU, for example, may require an internal clock that is several times faster than the system I/O bus clock. Designers can use PLL technology to synthesize a higher frequency on-chip clock using the system clock as a reference. STD111 1-10 Samsung ASIC Introduction 1.4 Product Family 6) Deskew clock: Multiple chips on a printed circuit board or cores of different sizes within a single system on a chip experience clock skew. By using PLL or DLL technology to shift the phase of the reference clock within each chip or core, designers can minimize skew tune a system to perform up its potential. 7) Duty Ratio: the percentage of the period that the output is in a high state. 8) Output frequency range: The maximum output frequency range minus the minimum output frequency that is produced with an input signal for which the cell specifications still apply. Customer Service Samsung provides a full custom support for our customers need of analog cores. Samsung's worldwide sales offices and representatives give our customers a first-hand support for analog cores. And if needed, Samsung engineers are prepared to provide a fully customized total solution to satisfy our customers. Technical Support If our customers want to develop mixed-signal products, Samsung provides all technical support to meet customers needs. Mixed-signal design is quite different from pure logic design in terms of circuit design, techniques, layout and test methodology. Thus Samsung provides a successful technical guide and firmly support for all development steps. Definition of Analog Core Data Sheet Types Each product developed by Samsung will be supported by technical literature where the data sheets progress through the following levels of refinement 1. Core Preview Describes the main features and specifications for core that is under development. Some specifications such as exact pin-outs may not be finalized at time of publication.The purpose of this document is to provide customers with advance product planning information. 2. Preliminary Datasheet This is the first document completely describing a new core. It contains an features, application, timing diagram, theory of operation, core pin information, test guide, layout guide and AC/DC electrical information. This data sheet are based on prototype silicon performance and on worst case simulation models.The purpose of this data sheet is to provide ASIC customer with technical information sufficiently detailed to guarantee that they can safely begin active development. 3.Final Data sheet This is an updated version of preliminary data sheet reflecting actual performance of the final silicon. Updates include tighter specifications, more min. and max. values. The purpose of this data sheet is to communicate the confirmed performance of cores which have passed qualification, been fully characterized. Samsung ASIC 1-11 STD111 1.4 Product Family Introduction 1.4.2 INTERNAL MACROCELLS Internal Macrocells are the lowest level of logic functions such as NAND, NOR and flip-flop used for logic designs. There are about 471 different types of internal macrocells. They usually come in four levels of drive strength (0.5X, 1X, 2X and 4X). These macrocells have many levels of representations--logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, physical layout, and placement and routing model. 1.4.3 COMPILED MACROCELLS Compiled macrocells of STD111 consist of compiled memory and compiled datapath macrocells. 1.4.3.1 Compiled Memory Macrocells Memories in STD111 are fully user-configurable and are provided as a compiler. Two different types of memories are available in STD111. One is suitable for highdensity application with high-performance, called STD111-HD compiled memory. The other is suitable for low-power application, called STD111-LP compiled memory. In STD111-HD compiled memory, eight types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM, synchronous diffusion/metal-programmable ROM, multi-port asynchronous register file and synchronous first-in first-out memory. Synchronous memories have a fully synchronous operation at the rising-edge of clock and the duty-free cycle is available. Also, the bit-write capability is available. Asynchronous memories have a synchronous operation for a write enable signal during write mode and have an asynchronous operation for address signal during read mode. Multi-port asynchronous register file supports four kinds of configurations such as 2 port(1-read/1-write), 3 port(1-read/2-write and 2-read/1write) and 4 port (2-read/2-write). The first-in first-out memory which is widely used in communication buffering types of applications has also fully synchronous operation at the rising- edge of clock. On the other hand, in STD111-LP compiled memory, five types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM and synchronous diffusion/metal-programmable ROM. Synchronous memories are almost same as that of STD111-HD except that the duty-free cycle is not available. Asynchronous memory is same as that of STD111-HD. To dramatically reduce the power consumption in STD111-LP, some of lowpower techniques such as a partial activation architecture in cell array and a divided word-line structure was adopted, rather than STD111-HD. Basically in STD111-HD and STD111-LP, the power-down mode which significantly reduces the power dissipated during a read or write mode is provided. Also compiled memories have a standby mode except multi-port asynchronous register file and first-in first-out memory. While in standby mode, the data stored in the memory is retained, data outputs remain stable and the power is greatly reduced because memory operation is internally blocked while the memory contents and the data outputs are unaffected. STD111 1-12 Samsung ASIC Introduction 1.4 Product Family To improve the memory performance and to reduce the power consumption, 2bank architecture is provided except some memories such as dual-port synchronous static RAM, multi- port asynchronous register file and first-in first-out memory. In 2-bank architecture, only one bank is activated and the other bank is in standby mode. To support various memory shapes which are determined by the floorplan of a chip design, flexible memory aspect ratios are provided. For certain specific memory configuration, all types of timing, power and area values are provided by an automatic datasheet generator. To easily do interface to layout, the physical abstract data for Silicon Ensemble and Apollo, called phantom cell or black box, is provided. BIST(Built-In Self-Test) circuitry is currently available for most of STD111 compiled memories. BIST circuits are designed to detect a set of fault types that impact the functionality of memory and is generated by a softmacro-based BIST generator. The softmacro-based BIST generator generates both an individual BIST netlist for each memory and a shared BIST netlist for all memories used in a design. However, when several memories of the same or the different type area used in the design, if you generate the individual BIST netlist for each memory, there are some redundant blocks because the individual BIST netlist has same function. In this case, it would better use the shared BIST netlist to eliminate such redundancy and reduce area. 1.4.3.2 Compiled Datapath Macrocells Compiled datapath macro cells include Adder, Barrel Shifter and Multiplier. Adder performs the adding or adding/subtracting operation on the control of a mode selection signal. Barrel Shifter makes input data shift or rotate in the left/right direction. In the shift operation, the vacant bit can be padded with zero, MSB value, or external data. Multiplier performs the 2's compliment multiplication. One pipeline stage insertion is available to get a high operating frequency. They have two output drive strengths, which are equal to the 1X and 2X-Drive in the primitive cell library. The hard macro cells are built through the Apollo, placement and routing tool from Avant!. All the leaf cells have the same physical configuration compatible with the primitive cell library. It allows that any primitive cell can be used as a bit slice cell in the datapath module design. We provide two kinds of engineering design services. One is to support additional compiled datapath macrocells such as ALUs, Comparators, Priority encoders, Incrementers and Decrementers, and so on. Another is to make hardwired datapath module design which provides a regular structured layout. Samsung ASIC 1-13 STD111 1.4 Product Family Introduction 1.4.4 INPUT/OUTPUT CELLS There are about seven hundreds different I/O buffers. Each I/O cell is implemented solely on the basic I/O cell architecture which forms the periphery of a chip. A test logic is provided to enable the efficient parametric (threshold voltage) testing on input buffers including LVCMOS and TTL level converters, Schmitt trigger input buffers, clock drivers and oscillator buffers. Pull-up and pull-down resistors are optional features. Three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1mA to 12mA for 2.5V, 3.3V drive and from 1mA to 3mA for 5.0V tolerant drive. One or two levels of slew rate controls are provided for each buffer type (except 1mA, 2mA and 3mA buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. Bi-directional buffers are combinations of input buffers and output buffers (tristate and open drain) in a single unit. The I/O structure has been fully characterized for ESD protection and latch-up resistance. For user's convenience, STD111 library provides 100K pull-down and pull-up resistance respectively. 1.4.4.1 I/O Applications To support mixed voltage environments, LVTTL, LVCMOS and Schmitt trigger I/ O cells are available at 2.5V, 3.3V interface and 5V tolerant interface. The I/O application diagram is as follows. Figure 1-6. I/O Applications 2.5V 2.5V C B 2.5 T S 3.3V C 3.3/ 5V tolerant Internal Circuit operating voltage: 2.5V 1.4.4.2 D 3.3V B S T T D Input Buffer 2.5 3.3 Output Buffer I/O Cell Drives Options To provide designers with the greater flexibility, each I/O buffer can be selected among various current levels (e.g., 1mA, 2mA,..., 12mA). The choice of currentlevel for I/O buffers affects their propagation delay and current noise. The slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. The output edge rate can be slowed down by selecting the high slew rate control cells. STD111 1-14 Samsung ASIC Introduction 1.4 Product Family STD111 provides three different sets of output slew rate controls. Only one I/O slot is required for any slew rate control options. 1.4.4.3 5V Tolerant I/O Buffers STD111 I/O library is based on a process which has the most optimum performance in 2.5V. In this process, voltage more than 3.6V are not allowed at the gate oxide because of a reliability problem. And a special circuit is adopted in order to make pin voltage tolerable up to 5.25V and to offer TTL interface driving up to 3mA. Obviously, this circuit is constructed not to permit more than 3.6V at the gate oxide. The external circuit diagram is as follows. The maximum external tolerance of this buffer is 5.25V. It can be used as a 3.3V normal buffer. Figure 1-7. 5V Tolerant I/O Buffers 3.3V 3.3V 5.0V Output voltage 3.3V Open drain output 5V tolerant input Tri-state output TTL Input Bi-directional I/O TTL Input 0.25m 2.5V process Normal 5V process 1.4.4.4 PCI Buffers PCI buffers are designed for PCI local bus application which is an industrystandard, high-performance 32bit or 64bit bus architecture. Samsung ASIC offers input, output, bi-directional PCI buffers for 33MHz and 66MHz operation. These buffers are compliant with PCI local bus specification 2.1. 1.4.4.5 USB (Universal Serial Bus) Buffers Various kinds of peripheral equipment such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. However, it is not easy to connect and use them properly in the computer. USB specification established late in 1995 is a good solution for this problem, providing facile method of an expansion. Samsung ASIC offers full speed and low speed USB buffers that complies with Universal Serial Bus specification 1.0, 1.1. 1.4.4.6 Other Buffers Samsung ASIC can support various kinds of buffers such as HSTL, SSTL, AGP, PECL, LVDS, and so on. For more information please contact us. Samsung ASIC 1-15 STD111 1.5 Timings Introduction 1.5 Timings 1.5.1 WIRE LENGTH LOAD Table 1-1. shows the equivalent standard load matrix for 4-layer and 5-layer metal interconnect. The equivalent standard load values are function of gate count and fanout. These values are based on capacitive loading and are used in wire length estimates which affect propagation delay. Table 1-1. Gates Count Equivalent Standard loads for 4-layer and 5-layer Metal Interconnect Fanouts 1 2 3 4 5 6 7 8 16 32 64 5000 0.701 1.357 2.312 3.093 3.609 4.247 4.755 6.622 17.348 27.615 48.295 10000 0.926 1.774 3.365 4.660 5.423 6.353 7.327 9.203 18.092 28.876 50.533 50000 2.536 4.990 7.526 9.980 10.165 10.879 12.722 13.798 21.501 29.252 51.190 100000 2.780 5.643 8.425 11.207 11.429 12.247 14.168 16.355 24.808 32.825 57.446 150000 7.770 10.361 12.952 13.724 14.279 14.700 15.732 17.988 24.098 38.524 77.049 200000 8.180 10.907 13.633 14.451 15.035 15.478 16.561 18.937 25.330 40.496 80.963 300000 8.998 11.998 14.997 16.087 16.697 17.161 18.343 20.955 27.994 44.696 89.297 400000 9.816 13.088 16.247 17.360 18.057 18.586 19.887 22.677 30.262 48.227 96.358 500000 10.951 14.601 18.252 19.468 20.229 20.807 22.252 25.431 32.210 51.345 102.531 600000 11.723 15.632 19.650 20.930 21.730 22.338 23.880 27.339 33.134 52.828 105.472 800000 13.507 18.010 22.834 24.270 25.165 25.847 27.615 31.704 35.807 57.110 113.982 1000000 15.174 20.232 25.809 27.392 28.376 29.127 31.104 35.779 38.289 61.088 121.885 1500000 19.743 26.325 33.911 35.904 37.138 38.085 40.643 46.899 45.765 73.055 145.688 2000000 24.024 32.032 41.504 43.880 45.352 46.480 49.581 57.320 52.758 84.249 167.954 2500000 28.030 37.374 48.611 51.347 53.036 54.338 57.946 67.072 59.291 94.706 188.751 3000000 31.775 42.367 55.254 58.326 60.221 61.682 65.764 76.187 65.385 104.459 208.150 4000000 36.455 48.606 63.391 66.915 69.090 70.765 75.450 87.407 75.013 119.844 238.804 4500000 38.642 51.522 67.194 70.930 73.235 75.011 79.978 92.651 79.513 127.034 253.132 5000 0.666 1.289 2.197 2.938 3.429 4.035 4.517 6.291 16.480 26.235 45.880 10000 0.880 1.686 3.196 4.427 5.152 6.036 6.961 8.743 17.188 27.432 48.007 50000 2.409 4.740 7.150 9.481 9.657 10.335 12.086 13.109 20.426 27.789 48.630 100000 2.642 5.361 8.004 10.647 10.857 11.634 13.555 15.537 23.568 31.184 54.574 150000 7.382 9.843 12.304 13.038 13.565 13.965 14.945 17.089 22.893 36.598 73.197 200000 7.770 10.361 12.952 13.729 14.283 14.705 15.733 17.990 24.064 38.471 76.915 300000 8.548 11.398 14.247 15.283 15.862 16.302 17.426 19.908 26.595 42.461 84.832 400000 9.326 12.433 15.434 16.492 17.155 17.656 18.892 21.543 28.749 45.816 91.512 500000 10.403 13.871 17.339 18.495 19.218 19767 21.139 24.160 30.599 48.778 97.404 600000 11.137 14.850 18.667 19.883 20.643 21.220 22.686 25.972 31.477 50.187 100.199 800000 12.832 17.110 21.692 23.056 23.908 24.555 26.235 30.119 34.016 54.255 108.284 1000000 14.415 19.220 24.519 26.022 26.957 27.670 29.549 33.990 36.375 58.034 115.790 1500000 18.756 25.009 32.216 34.109 35.282 36.181 38.611 44.554 43.477 69.403 138.404 2000000 22.823 30.431 39.429 41.687 43.084 44.156 47.102 54.454 50.120 80.036 159.556 2500000 26.629 35.505 46.180 48.779 50.385 51.621 55.049 63.718 56.326 89.971 179.313 3000000 30.186 40.249 52.491 55.410 57.211 58.598 62.476 72.377 62.115 99.237 197.743 4000000 34.633 46.176 60.221 63.569 65.635 67.227 71.678 83.036 71.262 113.852 226.863 5000000 38.832 51.777 67.527 71.279 73.597 75.382 80.372 93.108 79.907 127.662 254.382 6000000 43.542 58.057 75.716 79.926 82.525 84.525 90.121 104.403 89.598 143.146 285.238 4LM 5LM STD111 1-16 Samsung ASIC Introduction 1.5 Timings 1.5.2 TIMING PARAMETERS This section discusses issues involving timing parameters. 1.5.2.1 Transition Time Figure 1-8. shows the definition of rise transition time (tR) and fall transition time (tF). Transition time is defined as the delay between the time when the input (output) signal voltage level is 10% of supply voltage (VDD) and the time of the input (output) signal voltage level is 90% of VDD. Figure 1-8. Rise and Fall Transition Times VDD 90% 90% 10% 10% tR 1.5.2.2 tF Propagation Delays Figure 1-9. shows the definition of propagation delays. Propagation delay is defined as the delay between the time when the input signal voltage level is 50% of supply voltage (VDD) and the time when the output signal voltage level is 50% of VDD. Figure 1-9. Propagation Delay In 50% In Out tPLH 50% tPHL 50% 50% Out In VDD In 50% 50% tPHL tPLH Out 50% 50% Out Samsung ASIC 1-17 STD111 1.5 Timings Introduction 1.5.2.3 Setup / Hold Time Figure 1-10. shows the definition of setup time and hold time. The setup timing check is defined as the minimum interval which a data signal must remain stable before active transition of a clock. Any change to the data signal within this interval results in a timing violation. The hold timing check is defined as the minimum interval which a data signal must remain stable after active transition of a clock. Any change to the data signal within this interval results in a timing violation. Figure 1-10. Setup and Hold Times 50% D 50% 50% CK tSU tHD 1.5.2.4 Recovery Times Figure 1-11. shows the definition of recovery time. A recovery timing check measures the time between the release of an asynchronous control signal from the active state to the next active clock edge. For example, the time between RN and the CK of FD2 cell. If the active edge of the CK occurs too soon after the release of the RN, the state of the FD2 becomes uncertain. The state can be the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-11. Recovery Time 50% RN 50% CK tRC STD111 1-18 Samsung ASIC Introduction 1.5 1.5.2.5 Timings Removal Times Figure 1-12. shows the definition of removal time. A removal timing check measures the time between the active clock edge and the release of an asynchronous control signal from the active state. For example, the time between RN and the CK of FD2 cell. If the release of the RN occurs too soon after the active edge of the clock, the state of the FD2 becomes uncertain. The uncertainty can be caused by the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-12. Removal Time 50% RN 50% CK tRM 1.5.2.6 Minimum Pulse Widths Figure 1-13. shows the definition of minimum pulse width. The minimum pulse width timing check is the minimum allowable time for the positive (high) or negative (low) phase of each cycle. Figure 1-13. Minimum Pulse Width 50% CK tPWH tPWL 1.5.2.7 Minimum Period Figure 1-14. shows the definition of minimum period. The minimum period timing check is the minimum allowable time for one complete cycle of the signal. Figure 1-14. Minimum Period 50% CK tPRD Samsung ASIC 1-19 STD111 1.5 Timings Introduction 1.5.3 TEMPERATURE AND SUPPLY VOLTAGE The next figure describes propagation delay derating factors (KT, KV) as a function of on-chip junction temperature (TJ) and supply voltage (VDD). As a result of power dissipation, the junction temperature is generally higher than the ambient temperature. The temperature of the die inside the package (junction temperature, TJ) is calculated using chip power dissipation and the thermal resistance to the ambient temperature (JA) of the package. Information on package thermal performance can be obtained from Samsung application engineers. Figure 1-15. Effect of Temperature and Supply Voltage on Propagation Delay Temperature (TJ) KT 1.144 1.087 1.065 1.000 0.964 0.906 -40 0 25 70 85 125 (C) Supply Voltage (VDD) KV 1.074 1.000 0.941 2.3 STD111 1-20 2.5 2.7 (Volt) Samsung ASIC Introduction 1.5 Timings 1.5.4 BEST AND WORST CASE CONDITIONS A circuit should be designed to operate properly within a given specification level, either commercial or industrial. It is recommended that circuits be simulated for best case, normal case, and worst case conditions at each specification level. The following expressions also allow for the effect of process variation on circuit performance. Best case (Worst case): TBC (TWC) = KP x KT x KV x TNOM where TBC = Best case propagation delay TWC = Worst case propagation delay TNOM = Normal propagation delay (TJ = 25 oC, VDD = 2.5V and typical process) KP, KT, KV = Refer toTable 1-2., Table 1-3., and Table 1-4. 1.5.5 DERATING FACTORS OF STD111 The multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. Nominal data are provided for conditions of VDD = 2.5V, TJ = 25C and typical process. The derating factors of STD111 is as follows. Table 1-2. STD111 cell process derating factor (KP) Process Factor (KP) Table 1-3. Temp. (oC) KT Table 1-4. Typ Fast 1.200 1.0 0.849 STD111 cell temperature derating factor (KT) 125 85 70 25 0 -40 1.144 1.087 1.065 1.000 0.964 0.906 STD111 cell voltage derating factor (KV) Voltage (V) KV Samsung ASIC Slow 1-21 2.3 2.5 2.7 1.074 1.000 0.941 STD111 1.6 Delay Model 1.6 Delay Model Introduction The ASIC timing characteristics consist of the following components: * Cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. * Interconnection wire delay across the metal lines. * Timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. * Derating factors for junction temperature, power supply voltage, and process variations. Timing model for STD111 focuses on how to characterize cell propagation delay time accurately. To accomplish this goal, 2-dimensional table look-up delay model has been adopted. The index variables of this table are input waveform slope and output load capacitance. See the figure below. Samsung ASIC design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.25m cell-based products. Figure 1-16. 2-Dimensional Table Delay Model Propagation Delay [ns] 1.5 1.0 Load Cap [pF] 0.5 1.0 2.0 3.0 0.4 0.8 1.2 Input Waveform Slope [ns] STD111 1-22 Samsung ASIC Introduction 1.6 Delay Model The Table 1-5. shows an example of this model for 2-input NAND cell. The data in this table are high-to-low transition delay times from one of the two input pins to output pin. The number of points and values of the index variables can differ for each cell. Table 1-5. \ CAP Table Delay Model Example 0.010 0.042 0.106 0.233 0.424 0.678 0.020 0.04146 0.08814 0.18023 0.36303 0.63784 1.00330 0.198 0.06338 0.11782 0.20862 0.39030 0.66461 1.02980 0.415 0.07617 0.14488 0.24869 0.42763 0.70005 1.06410 0.849 0.08747 0.17724 0.30697 0.50902 0.77668 1.13720 1.500 0.09268 0.20337 0.36332 0.60379 0.90022 1.25490 SLOPE Notice that 5-by-6 table is used. Delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. This general table delay model provides great flexibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. The other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. The figure below summarizes the features of Samsung ASIC's delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used.The slopes (tR, tF) and delay times (tPLH, tPHL) of all cell instances are calculated recursively. The input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. Pin to pin delays of cells and interconnection wires are supported. The effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. Figure 1-17. Features of Delay Model S1 A_Y CO1 CO2 B_Y S2 D Q CO3 S3 Samsung ASIC CK 1-23 STD111 1.7 Testability Design Methodology 1.7 Testability Design Methodology Introduction 1.7.1 SCAN DESIGN * * * Multiplexed scan flip-flop that minimizes the area or delay overhead needed to implement scan design. Automated design rules checking, scan insertion, and test pattern generation High fault coverage on synchronous designs 1.7.2 BOUNDARY-SCAN * * * * IEEE Std 1149.1 JTAG boundary-scan registers with primitive cells Boundary-Scan Description Language (BSDL) description for board testing Combination with internal scan design and core testing Boundary Scan Architecture A boundary scan architecture contains TAP (Test Access Port), TAP controller, instruction register and a group of test data registers. The instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to TAP, TDI and TDO signals. TAP controller selects the alternative instruction and test data register paths between TDI and TDO. The schematic view of the top level design of the test logic architecture is shown in the Figure 118. Figure 1-18. JTAG Test Access Port (TAP) Block Diagram TDI TAP Controller TMS TCK Mux Instruction Register LOGIC Bypass Register SYSTEM Device Identity Register Scannable Register TEST ACCESS PORT (TAP) TDO Multiplexer Boundary Scan Path STD111 1-24 Samsung ASIC Introduction 1.7 Testability Design Methodology Boundary Scan Functional Block Descriptions TAP (Test Access Port) TAP is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. It includes three inputs (TCK; Test Clock Signal, TMS; Test Mode Signal and TDI; Test Data Input) and one output (TDO; Test Data Output) required by the test logic. An optional fourth input (TRSTN; Test Reset) is provided for the asynchronous initialization of the test logic. The values applied at TMS and TDI pins are sampled on the rising edge of TCK, and the value placed on TDO pin changes on the falling edge of TCK. TAP Controller TAP controller receives TCK, interprets the signals on TMS, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. Instruction Register/Instruction Decoder Test instructions are shifted into and held by the instruction register. Test instructions include a selection of tests to be performed or the test data register to be accessed. A basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. Test Data Registers Data registers include a bypass register, a boundary scan register, a device identification register and other design specific registers. Only the bypass- and boundary scan registers are mandatory; the rest are optional. Bypass register: The bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. It can be used to allow test data to flow through a given device to the other components in a product without affecting a normal operation. Boundary scan register: The boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. It also allows an access to component inputs and outputs when you test their logic or sample flow-through signals. Special boundary scan register macrocells are provided for this purpose. These special registers is discussed in the next section of next pages. Design-specific test data register: These optional registers may be provided to allow an access to design-specific test support features in the integrated circuit, such as self-test, scan test. Device identification register: This is an optional test data register that allows the manufacturer part number and variant of a components to be identified. The 32-bit identification register is partitioned into four fields: Device version identifier1st field Device part number Manufacturer's JEDEC number LSB Samsung ASIC The first four bits beginning from MSB 2nd field 16 bits 3rd field 11 bits 4th field 1 bit --tied in High 1-25 STD111 1.7 Testability Design Methodology Introduction The ASIC designer is free to fill the version and part number in any manner as long as the total twenty bits are used. Samsung's JEDEC code: 78 decimal = 1001110 Continuation field (4 bits) = 0000 Contents of device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 1 Users can define these two fields. Boundary Scan Register (connection of all boundary scan cells) Test Access Port (TAP) TDI Boundary Scan Path I/O Pad Instruction Register Test Data Register TMS TAP Controller Circuit Prior to Boundary Scan (Core Logic) TCK Bypass Register TDO MUX 1.7.3 BIST (BUILT-IN SELF-TEST) * * * STD111 Efficient test solution for compiled memory macrocells At speed and parallel testing of multiple memories Less routing overhead and test pin requirements 1-26 Samsung ASIC Introduction 1.8 Maximum Fanouts 1.8 1.8.1 INTERNAL MACROCELLS The maximum fanouts for STD111 primitive cells are as follows. Note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.198ns. Depending on the rise and fall times, the maximum fanout limitations can be varied case by case. In the following table the maximum fanout values for all pins of STD111 internal macrocells are listed. Table 1-6. Maximum Fanouts of Internal Macrocells (When input tR/tF = 0.198ns, one fanout (SL) = 0.01109pF) Cell Output Maximum Name Pin Fanouts ad2 ad2d2 ad2d4 ad2dh ad3 ad3d2 ad3d4 ad3dh ad4 ad4d2 ad4d4 ad4dh ad5 ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d2b ao211d4 ao211dh ao21d2 ao21d2b ao21d4 ao21dh ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2 ao222d2a ao222d2b ao222d4 ao222d4a ao22a Samsung ASIC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 51 104 206 24 52 103 207 24 51 103 201 24 25 51 207 24 15 10 103 30 103 207 7 48 102 206 11 23 14 103 207 13 8 103 208 22 28 102 102 206 206 23 1-27 Cell Name ao22d2 ao22d2a ao22d2b ao22d4 ao22d4a ao22dh ao22dha ao31 ao311 ao3111 ao3111d2 ao311d2 ao311d4 ao31d2 ao31d4 ao31dh ao32 ao321 ao321d2 ao321d4 ao322 ao322d2 ao322d4 ao32d2 ao32d4 ao33 ao331 ao331d2 ao331d4 ao332 ao332d2 ao332d4 ao33d2 ao33d4 ao4111 ao4111d2 busholder dc4 dc4i dc8i dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 Maximum Fanouts Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y0 Y1 Y2 Y3 YN0 YN1 YN2 YN3 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 Y Y Y Y Y Y Y Y Y Y Y Y Maximum Fanouts 47 47 102 206 206 11 11 22 14 9 103 103 207 46 206 10 17 13 103 207 12 103 207 102 206 16 12 103 207 11 102 207 102 206 8 103 10000 51 51 51 51 41 41 41 41 29 29 29 29 29 29 29 29 104 210 104 211 104 211 104 211 103 209 103 209 STD111 1.8 Maximum Fanouts Introduction Cell Name oak_duclk 10 oak_duclk 16 fa fad2 fadh fd1 fd1d2 fd1cs fd1csd2 fd1q fd1qd2 fd1s fd1sd2 fd1sq fd1sqd2 fd2 fd2d2 fd2cs fd2csd2 fd2q fd2qd2 fd2s fd2sd2 fd2sq fd2sqd2 fd3 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s fd3sd2 fd3sq fd3sqd2 fd4 fd4d2 fd4cs STD111 Output Pin Maximum Fanouts CK CKB CK CKB S CO S CO S CO Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN 222 222 223 223 52 51 103 103 24 23 51 51 102 102 51 51 102 102 51 102 51 51 102 102 51 103 51 51 104 103 51 49 103 100 51 103 51 51 104 103 51 103 51 51 103 103 51 51 102 102 51 102 51 51 103 102 51 103 51 50 103 102 51 49 1-28 Cell Name fd4csd2 fd4q fd4qd2 fd4s fd4sd2 fd4sq fd4sqd2 fd5 fd5d2 fd5s fd5sd2 fd6 fd6d2 fd6s fd6sd2 fd7 fd7d2 fd7s fd7sd2 fd8 fd8d2 fd8s fd8sd2 fds2 fds2d2 fds2cs fds2csd2 fds2s fds2sd2 fds3 fds3d2 fds3cs fds3csd2 fds3s Output Pin Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Maximum Fanouts 103 99 51 103 51 50 103 102 51 103 51 51 102 102 51 51 102 102 51 51 104 103 51 51 104 103 51 51 103 103 51 51 103 102 51 50 103 102 51 50 103 102 51 51 102 102 51 51 103 102 51 51 102 102 51 51 102 102 51 51 102 102 51 51 Samsung ASIC Introduction 1.8 Cell Name fds3sd2 fj1 fj1d2 fj1s fj1sd2 fj2 fj2d2 fj2s fj2sd2 fj4 fj4d2 fj4s fj4sd2 ft2 ft2d2 ha had2 hadh iv ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 ivdh ivt ivtd2 ivtd4 ivtd8 ivtd16 ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16 Samsung ASIC Output Pin Maximum Fanouts Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN S CO S CO S CO Y Y YN Y YN Y YN Y YN Y YN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 102 102 51 51 103 103 51 51 103 102 51 51 103 103 51 51 103 102 51 51 102 103 51 50 103 102 51 51 103 103 51 51 104 103 24 23 52 48 49 45 147 97 99 90 295 194 199 105 156 211 308 414 853 23 48 101 203 407 824 48 101 203 407 824 1-29 Cell Name ld1 ld1d2 ld1a ld1d2a ld1q ld1qd2 ld2 ld2d2 ld2q ld2qd2 ld3 ld3d2 ld4 ld4d2 ld5 ld5d2 ld5q ld5qd2 ld6 ld6d2 ld6q ld6qd2 ld7 ld7d2 ld8 ld8d2 oak_ldi2 oak_ldi2d2 oak_ldi3 oak_ldi3d2 ls0 ls0d2 ls1 ls1d2 mx2 mx2d2 mx2d4 mx2dh mx2i mx2ia mx2id2 Maximum Fanouts Output Pin Q QN Q QN Q Q Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Y Y Y Y YN YN YN Maximum Fanouts 51 51 102 102 40 84 51 102 51 51 103 103 51 102 51 51 103 103 51 51 104 103 51 51 102 102 51 102 51 51 103 103 51 102 51 51 103 103 51 51 104 103 51 51 102 102 51 51 104 103 42 42 83 83 26 26 102 103 51 103 204 24 24 23 103 STD111 1.8 Maximum Fanouts Introduction Cell Name mx2id2a mx2id4 mx2id4a mx2idh mx2idha mx2ix4 mx2x4 mx3i mx3id2 mx3id4 mx4 mx4d2 mx4d4 mx8 mx8d2 mx8d4 nd2 nd2d2 nd2d4 nd2dh nd3 nd3d2 nd3d4 nd3dh nd4 nd4d2 nd4d2b nd4d4 nd4dh nd5 nd5d2 nd5d4 nd6 nd6d2 nd6d4 nd8 nd8d2 nd8d4 nid oak_nid10p nid16 nid2 oak_nid20p nid3 nid4 nid6 nid8 nidh nit nitd16 nitd2 nitd4 nitd8 nitn nitnd16 nitnd2 nitnd4 nitnd8 nr2 STD111 Output Pin Maximum Fanouts Cell Name 103 206 207 11 11 24 24 24 24 51 51 51 51 51 103 207 51 102 197 50 99 186 41 83 168 19 29 60 120 13 22 45 103 206 10 51 102 206 51 102 206 51 102 206 50 1451 790 97 2883 146 196 290 387 24 48 825 101 202 407 48 825 101 202 407 25 nr2a nr2d2 nr2d2b nr2d4 nr2dh nr3 nr3a nr3d2 nr3d2b nr3d4 nr3dh nr4 nr4d2 nr4d4 nr4dh nr5 nr5d2 nr5d4 nr6 nr6d2 nr6d4 nr8 nr8d2 nr8d4 oa21 oa211 oa2111 oa2111d2 oa211d2 oa211d2b oa211d4 oa211dh oa21d2 oa21d2b oa21d4 oa21dh oa22 oa221 oa221d2 oa221d4 oa222 oa2222 oa2222d2 oa2222d4 oa222d2 oa222d2b oa222d4 oa22a oa22d2 oa22d2a oa22d2b oa22d4 oa22d4a oa22dh oa22dha oa31 oa311 oa3111 oa3111d2 oa311d2 oa311d4 oa31d2 oa31d4 oa31dh oa32 YN YN YN YN YN YN0 YN1 YN2 YN3 Y0 Y1 Y2 Y3 YN YN YN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 1-30 Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Maximum Fanouts 52 51 102 206 12 16 33 33 102 206 7 51 103 206 23 51 103 208 51 103 208 51 102 204 25 24 20 102 49 103 206 11 51 102 206 11 23 22 103 206 17 13 102 207 34 103 207 25 47 50 103 206 207 11 11 16 15 15 102 102 206 32 206 7 15 Samsung ASIC Introduction 1.8 Cell Name oa321 oa321d2 oa321d4 oa322 oa322d2 oa322d4 oa32d2 oa32d4 oa33 oa331 oa331d2 oa331d4 oa332 oa332d2 oa332d4 oa33d2 oa33d4 oa4111 oa4111d2 or2 or2d2 or2d4 or2dh or3 or3d2 or3d4 or3dh or4 or4d2 or4d4 or4dh or5 or5d2 or5d4 scg1 scg1d2 scg2 scg2d2 scg3 scg3d2 scg4 scg4d2 scg5 scg5d2 scg6 scg6d2 scg7 scg7d2 scg8 scg8d2 scg9 scg9d2 scg10 scg10d2 scg11 scg11d2 scg12 scg12d2 scg13 scg13d2 scg14 scg14d2 scg15 scg15d2 scg16 Samsung ASIC Output Pin Maximum Fanouts Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 14 103 206 12 103 207 103 206 13 13 102 206 9 102 207 103 207 10 102 51 103 208 23 51 103 206 23 41 83 206 19 41 83 206 29 59 51 104 29 59 41 83 51 102 51 102 41 83 51 103 51 102 51 102 16 32 25 51 42 84 41 83 29 59 24 1-31 Cell Name Maximum Fanouts Output Pin scg16d2 scg17 scg17d2 scg18 scg18d2 scg19 scg19d2 scg20 scg20d2 scg21 scg21d2 scg22 scg22d2 scg23 scg23d2 xn2 xn2d2 xn2d4 xn3 xn3d2 xn3d4 xo2 xo2d2 xo2d4 xo3 xo3d2 xo3d4 Y Y Y Y Y Y Y Y Y Y Y Y Y S CO S CO Y Y Y Y Y Y Y Y Y Y Y Y Maximum Fanouts 49 41 83 29 59 24 48 25 51 16 33 24 49 51 51 103 103 52 103 205 50 100 194 52 103 205 50 100 194 1.8.2 I/O Cells The maximum fanouts for I/O cells are as follows. Table 1-7. Maximum Fanouts of I/O Cells (tR/tF = 0.198ns, one fanout (SL) = 0.01109pF) Cell Output Maximum Name Pin Fanouts phic phicd phicu phis phisd phisu phit phitd phitu phsosck1 phsosck17 phsosck2 phsosck27 phsoscm1 phsoscm16 phsoscm2 phsoscm26 phsoscm3 phsoscm36 pic pic_abb picc_abb picd Y Y Y Y Y Y Y Y Y YN YN YN YN YN YN YN YN YN YN Y Y Y Y 163 163 163 163 163 163 163 163 163 115 116 117 117 117 117 124 124 243 243 79 79 81 79 STD111 1.8 Maximum Fanouts Introduction Cell Name picen_abb picu pis pisd pisu psosck1 psosck2 psoscm1 psoscm2 ptic pticd pticu ptis ptisd ptisu ptit ptitd ptitu STD111 Output Pin Maximum Fanouts Y Y Y Y Y YN YN YN YN Y Y Y Y Y Y Y Y Y 78 79 78 78 78 117 117 43 152 163 163 163 163 163 163 163 163 163 1-32 Samsung ASIC Introduction 1.8 Maximum Fanouts 1.8.3 CK Cell Max Fanout STD111 maximum fanout for CK cells <Condition> * VDD = 2.5V * Fanout = 0.00813pF (= input cap for CK pin of FD1) * Standard Load (SL) = 0.01109pF * Input slope = 0.198ns * Max output transition time (mott) = 1.5ns * Maximum frequency 200MHz * Net length (m/fanout): branch net length for each fanout except trunk Table 1-8. Maximum Fanout for CK Cells Trunk width (m) Net length (m/fanout) Trunk length (m) ck2 ck4 ck6 ck8 Table 1-9. 8 20 5000 87 251 408 555 200 10000 1 151 286 403 5000 27 79 128 175 10000 48 90 127 In case that interconnection is not considered 237 472 709 944 Maximum Fanout for NID Cells Trunk width (m) Net length (m/fanout) Trunk length (m) nid nid2 nid3 nid4 nid6 nid8 nid16 oak_nid10p oak_nid20p 0.44 8 20 200 5000 15 34 48 67 79 102 114 123 10000 5000 6 17 38 59 137 246 420 10000 10 29 97 172 267 In case that interconnection is not considered 50 97 146 196 290 387 790 1451 2883 For high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis. Samsung ASIC 1-33 STD111 1.9 Package Capability By Lead Count 1.9 Introduction Package Capability By Lead Count Package Lead Inductance SOP/SSOP (Small Outline Package) Lead Count 8 3.9 x 8.7mm < 2nH 3.9 x 9.9 mm < 4nH 4.0 x 5.1mm < 2nH 4.4 x 6.9 mm < 3nH 4.4 x 6.9 mm < 3nH 5.3 x 3.0 mm < 3nH 5.3 x 7.2 mm < 3nH 5.3 x 10.2 mm < 4nH 5.3 x 15.6 mm < 5nH 5.4 x 14.1 mm < 5nH 7.5 x 18.4 mm < 8nH 12.6 x 29.0mm < 20nH 12.7 x 29.0 mm < 16nH TSOP/TSSOP (Thin SOP) 4.4 x 3.0mm < 3nH 4.4 x 9.7 mm < 3nH 6.1 x 9.7mm < 3nH 6.1 x 14.0 mm < 6nH 10.2 x 18.9 mm < 8nH 10.2 x 21.4 mm < 7nH 10.2 x 22.6 mm < 7nH 12.0 x 20.0mm < 6nH 12.4 x 16.4 mm < 7nH PSOP/PSSOP (Power SOP) STD111 < 3nH < 3nH < 3nH < 6nH 20 24 28 44 56 70 8 28 32 44 48 54 56 66 8 3.9 x 9.9 mm 6.1 x 7.64 mm 7.6 x 12.8 mm 11.0 x 15.9 mm 16 16 20 1-34 Samsung ASIC Introduction Package Lead Inductance QFP (Quad Flat Package) 7 x 7 mm < 3nH 10 x 10 mm < 5nH 12 x 12 mm < 5nH 14 x 14 mm < 6nH 14 x 20 mm < 12nH 24 x 24 mm < 11nH 28 x 28 mm < 17nH 32 x 32 mm < 15nH TQFP (Thin Quad Flat Package) 7 x 7 mm < 4nH 12 x 12 mm < 5nH 14 x 14 mm < 5nH 14 x 20 mm < 10nH 20 x 20 mm < 9nH 24 x 24 mm < 11nH 28 x 28 mm < 13nH PLCC (Plastic Leaded Chip Carrier) 16.6 x 16.5mm <5nH 29.3 x 29.3 mm < 13nH Package Lead Inductance SBGA (Super BGA) Lp/g Lsig 27 x 27 mm < 3nH < 7nH 31 x 31 mm < 3nH < 8nH 35 x 35 mm < 3nH < 8nH 40 x 40 mm < 3nH < 9nH 42.5 x 42.5 mm < 3nH < 9nH 45 x 45 mm < 3nH < 9nH PBGA (Plastic BGA) Lp/g Lsig 14 x 22 mm < 4nH <9nH 15 x 15 mm < 4nH < 13nH 23 x 23 mm < 4nH < 18nH 27 x 27 mm < 4nH < 21nH 31 x 31 mm < 4nH < 13nH 35 x 35 mm < 4nH < 14nH PBGA (Plastic BGA) Lp/g Lsig 14 x 22 mm < 4nH <10nH 15 x 15 mm < 4nH < 13nH 23 x 23 mm < 4nH < 18nH 27 x 27 mm < 4nH < 21nH 31 x 31 mm < 4nH < 13nH 35 x 35 mm < 4nH < 14nH Samsung ASIC 1.9 Package Capability By Lead Count 44 48 64 80 Lead Count 100 128 160 208 160 176 208 240 256 32 48 80 100 144 44 84 Lead Count 256 304 352 432 560 600 119 121 169 204 208 217 225 249 256 272 300 388 420 456 304 316 324 329 352 1-35 360 385 STD111 1.10 Power Dissipation 1.10 Power Dissipation Introduction 1.10.1 ESTIMATION OF POWER DISSIPATION IN CMOS CIRCUIT CMOS circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. However, the recent revolution in a CMOS technology that allows very high gate density has changed the way the power dissipation should be understood. The power dissipation in a CMOS circuit is affected by various factors such as the number of gates, the switching frequency, the loading on the output of a gate, and so on. Power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. Propagation delays and reliability of the device also depend on power dissipation that determines the temperature at which the die operates. To obtain high speed and reliability, designers must estimate power dissipation of the device accurately and determine the appropriate environments including the package and system cooling methods. This section describes the concepts of two types of power dissipation (static and dynamic) in a CMOS circuit, the method of calculating those in the Samsung STD111 library. 1.10.2 STATIC (DC) POWER DISSIPATION There are two types of static or DC current contributing to the total static power dissipation in CMOS circuits. One is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. There is no DC current path from power to ground in a CMOS because one of the transistor pair is always off, therefore, no static current except the leakage current flows through the internal gates of the device. The amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. The other is DC current that flows through the input and output buffers when the circuit is interfaced with other devices, especially TTL. The current of pull-up/ pull-down transistor in the input buffers is about 33A (at 3.3V) and 25A (at 2.5V) typically, which is also negligible. Therefore, only DC current that the output buffers source or sink has to be counted to estimate the total static power dissipation. DC power dissipation of output and bi-directional buffers is determined by the following formula: n n PDC_OUTPUT [mW] = ( VOL(k) x IOL(k) x tL(k) ) + ( ( VDD - VOH(k) ) x IOH(k) x tH(k) ) T k = 1 k=1 n n PDC_BI [mW] = ( VOL(k) x IOL(k) x tL (k) ) + ( ( VDD - VOH (k) ) x IOH(k) x tH(k) ) x Sout T k = 1 k=1 where, n = Number of output and bidirectional buffers T = Total operation time in output mode tH = The sum of logic high state time tL = The sum of logic low state time tL + tH = T (Supposed that all output and bidirectional buffers have just logic high or low state) Sout is the output mode ratio of bidirectional buffers (typically 0.5) STD111 1-36 Samsung ASIC Introduction 1.10 Power Dissipation 1.10.3 DYNAMIC (AC) POWER DISSIPATION When a CMOS gate changes its state, it draws switching current as a result of charging or discharging a load capacitance, CL. The energy associated with the switching current for a node capacitance, CL, is CL x V DD 2 where VDD is the power supply voltage. In addition to the power dissipated by the load capacitance, CMOS circuits consume power due to the shortcircuit current flowing through a temporary VDD-to-ground path during switching. The dynamic power dissipation for an entire chip is much more complicated to estimate since it depends on the degree of switching activity of the circuit. Samsung has found that the degree of switching activity is 10% on the average and recommends this number to be used in estimating the total dynamic power dissipation. 1.10.4 POWER DISSIPATION IN STD111 This section describes the equations on how to estimate the power dissipation in STD111. As explained in the previous section, the total power dissipation (PTOTAL) consists of static power dissipation (PDC) and dynamic power dissipation (PAC). PTOTAL = PAC + PDC PDC is negligible in case of CMOS logic. The dynamic power dissipation is caused by three components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bidirectional buffers (PAC_BI), and internal cells (PAC_INTERNAL). PAC = PAC_ INPUT + PAC_OUTPUT + PAC_BI + PAC_INTERNAL Each term mentioned above is characterized by the following equations: N_2.5V_input PAC_INPUT [mW] = 2.5 x j N_3.3V_input N_total_input Fj Fk I I x ---------- x S j + 3.3 x x ---------- x Sk + 6.25 x (0.001 x Si x Fi x Ci_inload) j_eq_p k_eq_p 100 100 k N_2.5V_output PAC_OUTPUT [mW] = 2.5 x Fi I x - x Si + 3.3 x i_eq_p -------- 100 i N_3.3V_output i N_2.5V_output 6.25 x j Fj I x - x S j + j_eq_p -------- 100 N_3.3V_output ( 0.001 x Si x Fi x Ci_outload ) + 10.89 x i ( 0.001 x S j x F j x Cj_outload ) j PAC_BI [mW] = PAC_BI_INPUT x ( 1 - Sout ) + PAC_BI_OUTPUT x Sout N_2.5V_bi PAC_BI_INPUT [mW] = 2.5 x j N_3.3V_bi N_total_bi Fj Fk I x - x S j + 3.3 x Ik_eq_p x ---------- x Sk + 6.25 x ( 0.001 x Si x Fi x Ci_inload ) j_eq_p -------- 100 100 k N_2.5V_bi PAC_BI_OUTPUT [mW] = 2.5 x Fi I x - x Si + 3.3 x i_eq_p -------- 100 i N_3.3V_bi i N_2.5V_bi 6.25 x j Fj I x - x S j + j_eq_p -------- 100 N_3.3V_bi ( 0.001 x Si x Fi x Ci_outload ) + 10.89 x i ( 0.001 x Si x Fi x Ci_outload ) j N_macro PAC_INTERNAL [mW] = 0.001 x ( 0.3018 x S + 0.0331 ) x G x F + ( 0.001 x Pi x Fi ) j Samsung ASIC 1-37 STD111 1.10 Power Dissipation Introduction where N_2.5V_input is the number of 2.5V interface input buffers used N_3.3V input is the number of 3.3V interface input buffers used, N_total_input = N_2.5V_input + N_3.3V input N_2.5V_output is the number of 2.5V interface output buffers used, N_3.3V_output is the number of 3.3V interface output buffers used, N_2.5V_bi is the number of 2.5V interface bidirectional buffers used, N_3.3V_bi is the number of 3.3V interface bidirectional buffer used, N_macro is the number of macro cells used, G is the size of the design in gate count, F is the operating frequency in MHz, S is the estimated degree of switching activity (typically 0.1 for internal and 0.5 for I/O), Sout is the output mode ratio of bidirectional buffers (typically 0.5), C is the load capacitance in pF. P is the characterized power for the i-th hard macro block (W/MHz) 1.10.5 TEMPERATURE AND POWER DISSIPATION The total power dissipation, PTOTAL can be used to find out the device temperature by the following equation: JA = (TJ - TA) / PTOTAL where JA is the thermal impedance, TJ is the junction temperature of the device, TA is the ambient temperature. Thermal impedances of the Samsung packages are given in the following table. The junction temperature, obtained by multiplying PTOTAL by the appropriate JA and adding TA, determines the derating factor for the propagation delays and also indicates the reliability measures. Hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. Table 1-10. Thermal Impedances of Samsung Plastic Packages SOP/TSOP Pin Number JA[C/W] 20 24 28 32 44 50 54 62 66 63 58 41-44 46-56 44-71 39-59 34-56 27-33 34-46 QFP Pin Number JA[C/W] 44 48 80 100 120 128 160 208 240 256 51-62 43-56 43-74 27-61 33-47 43-51 29-51 22-43 28-47 29-42 TQFP/LQFP Pin Number JA[C/W] 32 64 100 144 160 176 208 256 68-70 47 37-70 38 35-62 31-34 37-56 30-42 PBGA Pin Number JA[C/W] 272 388 356 (TEPBGA) 452 (TEPBGA) 19-22 16-19 16 14 SBGA Pin Number JA[C/W] STD111 256 304 352 432 600 14.1 13.1 11.7 10.2 8.3 1-38 Samsung ASIC Introduction 1.11 VDD/VSS Rules And Guidelines 1.11 VDD/VSS Rules And Guidelines There are three kinds of VDD and VSS in STD111, providing power to internal and I/O area. * * * Core logic - VDD2I, VSS2I Pre-driver (I/O area) - VDD2P, VDD3P, VSS2P, VSS3P Output-drive (I/O area) - VDD2O, VDD3O, VSS2O, VSS3O The number of VDD and VSS pads required for a specific design depends on the following factors: * * * * Number of input and output buffers Number of simultaneous switching outputs Number of used gates and simultaneous switching gates Operating frequency 1.11.1 BASIC PLACEMENT GUIDELINES The purpose of these guidelines is to minimize IR drop and noise for reliable device operations. * Core logic and pre-driver VDD/VSS pads should be evenly distributed on all sides of the chip. * If you have core block demanding high power (compiled memory, analog), extra power pads should be placed on that side. * Power pads for SSO group should be evenly distributed in the SSO group. * Do not place the quiet signal (analog, reference) or analog power (VDDA/ VSSA) or bi-directional buffer next to a SSO group. * The opposite types of power pads (VDD/VSS) should be placed as close as possible. * If it is possible, do not place power pads (VDD/VSS) at the corner of the chip. 1.11.2 VDD2I/VSS2I ALLOCATION GUIDELINES The purpose of these guidelines is to ensure that the minimum number of core logic power pad pairs meeting the electromigration current limit are used. The number of VDD2I/VSS2I pads required for a specific design is determined by the function of the operating frequency of a chip. Samsung ASIC * VDD2I bus width and the number of pads are equal to those of VSS2I * VDD2I/VSS2I buses and pads should be distributed evenly in the core and on each side of the chip. * The total number of core logic VDD2I pads is equal to that of VSS2I pads. 1-39 STD111 1.11 VDD/VSS Rules And Guidelines Introduction The number of VDD2I/VSS2I pad pairs required for a design can be calculated from the following expression: The number of VDD2I/VSS2I pad pairs = 0.001 x ( 0.1207 x S + 0.0133 ) x G x F + N_macro ( Pi x Fi) lem round - up i where, G = The core (excluding hard macro blocks) size in the gate counts S = The switching ratio (typically = 0.1) F = Operating frequency (MHz) Pi = Characterized current for the i-th hard macro block (mA/MHz) Fi = Operating frequency for the i-th hard macro block (MHz) Iem = Current limit per VDD/VSS pad pairs based on ElectroMigration rule (80mA) For reliable device operation and minimize IR voltage drop, minimum number of VDD2I/VSS2I power pad pairs is 4. Extra power may be needed for the demanding high power macro blocks (SRAM, analog block...). 1.11.3 VDD2P/VSS2P (VDD3P/VSS3P) ALLOCATION GUIDELINES. These guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. The number of VDD2P/VSS2P (VDD3P/VSS3P) pads required for a design can be calculated from the following expression: leq_p Number_ of_VDD2P/VSS2P(VDD3P/VSS3P) pairs = ---------- round - up lem In above expression, Ieq_p = (Average current of input/output buffers and bi-direction pre-drivers at maximum operational I/O frequency) [mA] (Refer Table 1-11) N_input Ieq_p = i N_output N_bi Fi Fj Fk Fk I x ---------- + I j_eq_p_out x ---------- + Ik_eq_p_in x ---------- ( 1 - Sout ) + Ik_eq_p_out x ---------- x Sout eq_p_in 100 100 100 100 j k where N_input is the number of input buffers used, N_output is the number of output buffers used, N_bi is the number of bi-directional buffers used, F is the operating frequency in MHz, Sout is the output mode ratio of bi-directional buffers (typically 0.5), Iem = Current limit per VDD/VSS pad pairs based on electromigration rule. (80mA) Table 1-11. 2.5V Interface Input Buffer Type Ieq_p (mA) Output Pre-Driver Type Ieq_p (mA) STD111 Normal Slew rate B1-4 0.14 0.14 CMOS 0.35 Driver B6-8 0.27 0.25 B10-12 0.41 0.35 1-40 T1-4 0.24 0.25 CMOS Schmitt 0.36 Tristate T6-8 0.36 0.35 T10-12 0.53 0.45 Samsung ASIC Introduction 1.11 Table 1-12. 3.3V Interface Input Buffer Type Ieq_p Normal (mA) Tolerant Output Pre-driver Type Ieq_p (mA) Normal Tolerant Normal Slew rate CMOS 0.52 0.60 CMOS Driver B1-4 B6-8 0.25 0.46 0.28 0.37 - VDD/VSS Rules And Guidelines TTL 0.54 0.60 B10-12 0.55 0.46 - - T1-4 0.34 0.36 (T1,2,3) 0.50 Schmitt Trigger 0.54 0.51 Tristate T6-8 T10-12 0.51 0.60 0.45 0.55 - - For reliable device operation and minimum IR voltage drop, at least 4 pairs of VDD2P/VSS2P (VDD3P/VSS3P) power pads are needed. 1.11.4 VDD2O/VSS2O (VDD3O/VSS3O) ALLOCATION GUIDE SSO (Simultaneous Switching Output) current induced in power and ground inductance can cause system failure because of voltage fluctuations. For the calculation of output drive power pad numbers, we consider the SSO noise as well as the current limit based on electromigration. We may define the SSO as outputs switching simultaneously in 1ns windows, such as bus type buffers. NOTE: In case of heavy load, high frequency and low package inductance, the number of power pads for SSO block could be determined by electromigration rule rather than limit of SSO noise. So the number of power pads for SSO block should be determined as the worse one of the power pad number under the limit of SSO noise and that under the limit of electromigration rule. 1) Number of power pads for SSO block - Number of power pads for SSO block under the limit of SSO noise * Calculating the number of power pad for each SSO group from the following expressions: number_of_SSO 1 NVDDOeach_SSO = ---------------------------------------------- x Lpg x -------------------------NBvdd DSSO_mode number_of_SSO 1 NVSSOeach_SSO = ---------------------------------------------- x Lpg x -------------------------NBvss DSSO_mode In above formula, NVDDOeach_sso = Number of VDD2O (VDD3O) pad required for each SSO group NVSSOeach_sso = Number of VSS2O (VSS3O) pad required for each SSO group NBvdd = Number of buffers per VDD2O (VDD3O) power pad with 1nH lead inductance (Refer Table 1-15.) NBvss = Number of buffers per VSS2O (VSS3O) ground pas with 1nH lead inductance Lpg = Package lead frame inductance (refer to 1.9 package capability by lead count) Dsso_mode = DL_mode x DP_mode x DV_mode x DT_mode x DC_mode (Refer to Table 1-13. and Table 1-14.) DL_mode = Lead inductance derating factor DP_mode = Process derating factor DV_mode = Voltage derating factor DT_mode = Temperature derating factor DC_mode = Cload derating factor (*mode is either vdd or vss.) Samsung ASIC 1-41 STD111 1.11 VDD/VSS Rules And Guidelines Table 1-13. Item Package Lead Derating Equation (external 2.5V interface) Mode Equation DL_vdd DL_vss Process DP_vdd DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss Table 1-14. Item Package Lead DL_vdd Process DP_vdd DP_vss DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss STD111 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 1.0000 1.2549 1.7255 1.0000 1.2549 1.7451 - 0.8824 x voltage + 3.3235 - 0.5882 x voltage + 2.5882 - 0.8824 x voltage + 3.3235 - 0.5882 x voltage + 2.5882 0.0024 x temperature + 1.0000 0.0032 x temperature + 0.9786 0.0031 x temperature + 1.0000 0.0029 x temperature + 1.0071 0.0347 x Cload + 0.6525 0.0286 x Cload + 0.8369 0.0354 x Cload + 0.6456 0.0285 x Cload + 0.8544 Derating Equation (external 3.3V interface) Mode Equation DL_vss Voltage Introduction 0.0462 x Lpg + 1.1538 0.0231 x Lpg + 1.3846 0.0469 x Lpg + 0.7813 0.0313 x Lpg + 0.9375 1.0000 1.2537 2.2985 1.0000 1.1563 1.4063 - 1.2936 x voltage + 5.4328 - 0.4478 x voltage + 2.6119 - 0.4166 x voltage + 2.5000 - 0.4166 x voltage + 2.5000 0.0036 x temperature + 1.0000 0.0041 x temperature + 0.9878 0.0038 x temperature + 1.0000 0.0028 x temperature + 1.0227 0.0338 x Cload + 0.6618 0.0554 x Cload + 0.0146 0.0444 x Cload + 0.5556 0.0370 x Cload + 0.7778 1-42 Range 3nH Lpg 10nH 10nH Lpg 15nH 3nH Lpg 10nH 10nH < Lpg 15nH best typical worst best typical worst 2.3 voltage 2.5 2.5 < voltage 2.7 2.3 voltage 2.5 2.5 < voltage 2.7 -40 temperature 25 25 < temperature 125 -40 temperature 25 25 < temperature 125 10pF Cload 30pF 30pF < Cload 50pF 10pF Cload 30pF 30pF < Cload 50pF Range 3nH Lpg 10nH 10nH Lpg 15nH 3nH Lpg 10nH 10nH < Lpg 15nH best typical worst best typical worst 3.0 voltage 3.3 3.3 < voltage 3.6 3.0 voltage 3.3 3.3 < voltage 3.6 -40 temperature 25 25 < temperature 125 -40 temperature 25 25 < temperature 125 10pF Cload 30pF 30pF < Cload 50pF 10pF Cload 30pF 30pF < Cload 50pF Samsung ASIC Introduction Table 1-15. 1.11 VDD/VSS Rules And Guidelines NBvdd/NBvss Parameter (Process = best, Volt =2.7V/3.6V Temp. = 0C, Llead = 1nH) Normal Slew-Rate Medium (sm) Slew-Rate High (sh) Buffer Type pob1 (pot1) pob2 (pot2) pob4 (pot4) pob6 (pot6) pob8 (pot8) pob12 (pot12) phob1 (phot1) phob2 (phot2) phob4 (phot4) phob6 (phot6) phob8 (phot8) phob12 (phot12) ptot1 ptot2 ptot3 Voltage Type 2.5V Interface 3.3V Interface 5V Tolerant NBvdd NBvss NBvdd NBvss NBvdd NBvss 176 140 102 84 72 60 382 276 134 108 98 86 434 272 203 178 142 102 84 72 60 166 104 64 44 38 32 376 180 116 - - 160 142 116 96 - - 168 132 118 92 - - 160 142 116 96 - - 104 90 86 62 - - - - - 236 - - - - - 130 - - - - - 236 - - - - - 124 - NOTE: pob1 means 1mA output driver cell, and pob12 means 12mA output driver cell. * Calculating the number of required power pad for total SSO from the following expression: NVDDO1sso = NVDDOeach_sso NVSSO1sso = NVSSOeach_sso When there are SSO blocks which are not switching simultaneously with the others, only maximum value of NVDDO_each_sso/NVSSO_each_sso among those SSO block should be accounted. In the above formula, NVDDOsso = Number of VDD2O (VDD3O) pad per total SSO buffers NVSSOsso = Number of VSS2O (VSS3O) pad per total SSO buffers Samsung ASIC 1-43 STD111 1.11 VDD/VSS Rules And Guidelines Introduction - Number of power pads for SSO block under the limit of electromigration rule * Calculating the following expression: Ieq_o NVDDO2SSO NVSSO2SSO = ----------Iem N_SSO_output Ieq_o = N_SSO_bi ( 0.001 x Ci_outload x Vi x Fi x Si ) + i ( 0.001 x C j_outload x V j x F j x S j x S j_out ) j where N_SSO_output is the number of simultaneous switching output buffers used, N_SSO_bi is the number of simultaneous switching bi-directional buffers used, Coutload = Output load capacitance [pF] V = Operating voltage [V] F = Maximum I/O operating frequency [MHz] S = Switching ratio (typically 0.5) Sout = Output mode ratio of bidirectional buffers (typically 0.5) Iem = Current limit per VDD/VSS pad paris based on electromigration rule. (80mA) 2) Number of power pads for non-SSO block * Calculating the following expression: Ieq_o NVDDOnon_SSO NVSSOnon_SSO = ----------Iem N_non_SSO_output Ieq_o = N_non_SSO_bi ( 0.001 x Ci_outload x Vi x Fi x Si ) + i ( 0.001 x C j_outload x V j x F j x S j x S j_out ) j where N_non_SSO_output is the number of non-simultaneous switching output buffers used, N_non_SSO_bi is the number of non-simultaneous switching bi-directional buffers used, Coutload = Output load capacitance [pF] V = Operating voltage [V] F = Maximum I/O operating frequency [MHz] S = Switching ratio (typically 0.5) Sout = Output mode ratio of bidirectional buffers (typically 0.5) Iem = Current limit per VDD/VSS pad paris based on electromigration rule. (80mA) 3) Total number of power pads for VDD2O/VSS2O (VDD3O/VSS3O) * Calculating the following expressions: Number of VDD2O (VDD3O) = max ( NVDDO1SSO, NVDDO2SSO ) + NVDDOnon_SSO round-up Number of VSS2O (VSS3O) = max ( NVSSO1SSO, NVSSO2SSO ) + NVSSOnon_SSO round-up When open drain type buffers are used, you can consider using VSS2O (VSS3O) pads since they have current sink only. STD111 1-44 Samsung ASIC Introduction 1.12 Crystal Oscillator Consideration 1.12 Crystal Oscillator Consideration 1.12.1 OVERVIEW STD111 contains a circuit commonly referred to as an "on-chip oscillator." The on-chip circuit itself is not an oscillator but an amplifier which is suitable for being used as the amplifier part of a feedback oscillator. With proper selection of offchip components, this oscillator circuit performs better than any other types of clock oscillators. It is very important to select suitable off-chip components to work with the onchip oscillator circuitry. It should be noted, however, that Samsung cannot assume the responsibility of writing specifications for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the finished design in production, any more than a transistor manufacturer, whose data sheets show a number of suggested amplifier circuits, can assume responsibility for the operation, in production, of any of them. We are often asked why we don't publish a list of required crystal or ceramic resonator specifications, and recommend values for the other off-chip components. This has been done in the past, but sometimes with consequences that were not intended. Suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. Then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. Fearing that Samsung will not "guarantee operation" with 50ohm crystals, you order the expensive ones. In fact, Samsung guarantees only what is embodied within an Samsung product. Besides, there is no reason why 50ohm crystals couldn't be used, if the other off-chip components are suitably adjusted. Should we recommend values for the other off-chip components? Should we do for 50ohm crystals or 30ohm crystals? With respect to what should we optimize their selection? Should we minimize start-up time or maximize frequency stability? In many applications, neither start-up time nor frequency stability is particularly critical, and our "recommendations" are only restricting your system to unnecessary tolerances. It all depends on the application. 1.12.2 OSCILLATOR DESIGN CONSIDERATIONS ASIC designers have a number of options for clocking the system. The main decision is whether to use the "on-chip" oscillator or an external oscillator. If the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? The decisions have to be based on both economic and technical requirements. In this section we will discuss some of the factors that should be considered. Samsung ASIC 1-45 STD111 1.12 Crystal Oscillator Consideration Introduction 1.12.2.1 On-Chip Oscillator In most cases, the on-chip amplifier with the appropriate external components provides the most economical solution to the clocking problem. Exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. The external components that commonly used for CMOS gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, C1 and C2, and two resistor Rf and Rx as shown in the figure below. Figure 1-19. CMOS Oscillator Inside of a Chip C1 PADA Feedback Amplifier Rf C2 Rx PADY 1.12.2.2 Crystal Specifications Specifications for an appropriate crystal are not very critical, unless the frequency is. Any fundamental-mode crystal of medium or better quality can be used. We are often asked what maximum crystal resistance should be specified. The best answer to that question is the lower the better, but use what is available. The crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it can't be compensated for by appropriate selection of the capacitance, C1 and C2. Similar questions are asked about specifications of load capacitance and shunt capacitance. The best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such specifications are meaningful in your frequency tolerances are tighter than about 0.1%. Part of the problem is that crystal manufacturers are accustomed to talking "ppm" tolerances with radio engineers and simply won't take your order until you've filled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. Don't pay for 0.003% crystals if your actual frequency tolerance is 1%. STD111 1-46 Samsung ASIC Introduction 1.12 Crystal Oscillator Consideration 1.12.2.3 Oscillation Frequency The oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. The on-chip amplifier has little effect on the frequency, which is as it should be, since the amplifier parameterizes temperature and process dependent. The influence of the on-chip amplifier on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel C1 and C2, and the PADA-to-PADY (pin-to-pin) capacitance, which parallels the crystal. The input and pin-to-pin capacitances are about 7pF each. Internal phase deviations capacitance of 25 to 30pF. These deviations from the ideal have less effect in the positive reactance oscillator (with the inverting amplifier) than in a comparable series resonant oscillator (with the non-inverting amplifier) for two reasons: first, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. 1.12.2.4 C1 / C2 Selection Optimal values for the capacitors C1 and C2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-specific requirements on start-up time and frequency tolerance. Start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. Less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. As a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. Considerations of both start-up time and frequency stability over temperature suggest that C1 and C2 should be about equal and at least 15pF. (But they don't have to be either.) Increasing the value of these capacitances above some 40 or 50pF improves frequency stability. It also tends to increase the start-up time. These is a maximum value (several hundred pH, depending on the value of R1 of the quartz or ceramic resonator) above which the oscillator won't start up at all. If the on-chip amplifier is a simple inverter, the user can select values for C1 and C2 between some 15 and 50pF, depending on whether start-up time or frequency stability is the more critical parameter in a specific application. 1.12.2.5 Rf / Rx Selection A CMOS inverter might work better in this application since a large Rf (1megaohm) can be used to hold the inverter in its linear region. Logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. For that reason a resistor Rx (several k-ohm) is often added to the feedback network, as shown in Figure 1-19. At higher frequencies a 20 or 30pF capacitor is sometimes used in the Rx position, to compensate for some of the internal propagation delay. Samsung ASIC 1-47 STD111 1.12 Crystal Oscillator Consideration Introduction 1.12.2.6 Pin Capacitance Rf / Rx Selection Internal pin-to-ground and pin-to-pin capacitances, and PADA and PADY have some effect on the oscillator. These capacitances are normally taken to be in the range of 5 to 10pF, but they are extremely difficult to evaluate. Any measurement of one such capacitance necessarily include effects from the others. One advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. We would suggest that there is little justification for more precision than to assign them a value of 7pF (PADA-to-ground and PADA-to-PADY). This value is probably not in error by more than 3 or 4pF. The PADY-to-ground cap. is not entirely a "pin capacitance", but more like an "equivalent output capacitance" of some 25 to 30pF, having to include the effect of internal phase delays. This value varies to some extent with temperature, process, and frequency. 1.12.2.7 Placement of Components Noise glitches arising at PADA or PADY pins at the wrong time can cause a miscount in the internal clock-generating circuitry. These kinds of glitches can be produced through capacitive coupling between the oscillator components and PCB traces carrying digital signals with fast rise and fall times. For this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the PADA, PADY, and VSS pins. If possible, use dedicated VSS and VDD pin for only crystal feedback amplifier. 1.12.3 TROUBLESHOOTING OSCILLATOR PROBLEMS The first thing to consider in case of difficulty is that there may be significant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. Noise glitches, that are not present in the test jig but are in the application board, are another possibility. Capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. Inductive coupling is also doubtful, if there is strong current nearby. These problems are a function of the PCB layout. Surrounding oscillator components with "quit" traces (for example, VCC and ground) will alleviate capacitive coupling to signals having fast transition time. To minimize inductive coupling, the PCB layout should minimize the areas of the loops formed by oscillator components. The loops demanding to be checked are as follows: PADA through the resonator to PADY; PADA through C1 to the VSS pin; PADY through C2 to the VSS pin. It is not unusual to find that the ground ends of C1 and C2 eventually connect up to the VSS pin only after looping around the farthest ends of the board. Not good. Finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. Never underestimate the perversity of a software problem. STD111 1-48 Samsung ASIC